MTECH VLSI PROJECT LIST 2016-2017

SNO

                       PROJECT TITLES

year

 1

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

 2016

 2

Low power array multiplier using modified full adder

 2016

 3

Approximate Adder with Hybrid Prediction and Error Compensation Technique

 2016

 4

Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits

 2016

 5

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

 2016

 6

Low power high speed area efficient Error Tolerant Adder using gate diffusion input method

 2016
 7

Design of fast FIR filter using compressor and Carry Select Adder

 2016
 8

Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches

 2016
 9 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications  2016
10 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication  2016
11 RF Power Gating: A Low-Power Technique for Adaptive Radios  2016
12 Low-Power FPGA Design Using Memoization-Based Approximate Computing  2016

13

Method to Design Single Error Correction Codes With Fast Decoding for a Su bset of Critical Bits

 2016

14

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation

 2016

 15

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

 2016

 16

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

  2016
17

Digital Multiplierless Realization of Two-Coupled Biological Hindmarsh–Rose Neuron Model

2016

 18

 Arithmetic algorithms for extended precision using floating point expansions

 2016

 19

 A Novel Coding Scheme for Secure Communications in Distributed RFID Systems

 2016

 20

 A High Throughput List Decoder Architecture for Polar Codes

 2016

 21

 Performance/Power Space Exploration for Binary64 Division Units

 2016

 22

 High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)

 2016

 23

 Hybrid LUT/Multiplexer FPGA Logic Architectures

 2016

 24

 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

 2016

 25

 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

 2016

 26

 VLSI Design for Convolutive Blind Source Separation

 2016

 27

 A High-Speed FPGA Implementation of an RSD-Based ECC Processor

 2016

 28

 High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- LeMultipliersvel Mastrovito 

 2016

 29

 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

 2016

 30

 A Cellular Network Architecture With Polynomial Weight Functions

 2016

 31

 A Modified Partial Product Generator for Redundant Binary Multipliers

 2016

 32

 A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

 2016

 33

 Design and Analysis of Inexact Floating-Point Adders

 2016

 34

 Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design

 2016

 35

 Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression

 2016

 36

 An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

 2016

 37

Low-Pow er Parallel Chien Search Architecture Using a Two-Step Approach

 2016

 38

 Concept, Design, and Implementation of Reconfigurable CORDIC

 2016

 39

 On Efficient Retiming of Fixed-Point Circuits

 2016

 40

 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

 2016

 41

 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

 2016

 1 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers  2015

 2

Recursive Approach to the Design of a Parallel Self-Timed Adder

 2015

 3

Berger check and fault tollernce reversible arthimatic component design

 2015

 4

Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications

 2015

 5

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

 2015

 

 

 

 

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